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XA2C128 CoolRunner-II Automotive CPLD
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DS554 (v1.1) May 5, 2007
Product Specification Refer to the CoolRunnerTM-II Automotive CPLD family data sheet for architecture description. WARNING: Programming temperature range of TA = 0 C to +70 C.
Features
* AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade Guaranteed to meet full electrical specifications over TA = -40 C to +105 C with TJ Maximum = +125 C (Q-grade) Optimized for 1.8V systems Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation -- 1.5V to 3.3V Available in the following package options - 100-pin VQFP with 80 user I/O - 132-ball CP (0.5mm) BGA with 100 user I/O - Pb-free only for all packages Advanced system features - Fastest in system programming * 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management * DataGATE enable (DGE) signal control - Two separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes * Optional DualEDGE triggered registers * Clock divider (divide by 2,4,6,8,10,12,14,16) * CoolCLOCK - Global signal options with macrocell control * Multiple global clocks with phase selection per macrocell * Multiple global output enables * Global set/reset - Advanced design security - Open-drain output option for Wired-OR and LED drive - PLA architecture * Superior pinout retention * 100% product term routability across function block - Optional bus-hold, 3-state or weak pull-up on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels - Hot pluggable
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Description
The CoolRunner-II Automotive 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.
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(c) 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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XA2C128 CoolRunner-II Automotive CPLD The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II Automotive 128-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The CoolRunner-II Automotive 128-macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
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products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II Automotive CPLDs achieve both high-performance and low power operation.
Supported I/O Standards
The CoolRunner-II Automotive 128-macrocell device features LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Table 1: I/O Standards for XA2C128 IOSTANDARD Attribute Output VCCIO LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15(1) 3.3 3.3 2.5 1.8 1.5 Input VCCIO 3.3 3.3 2.5 1.8 1.5
RealDigital Design Technology
Xilinx CoolRunner-II Automotive CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II Automotive CPLDs employ RealDigital technology, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital technology employs a cascade of CMOS gates to implement sum of
(1) LVCMOS15 requires use of Schmitt-trigger inputs.
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ICC (mA)
10 0
0 50 100
DS554_092106
150
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical ICC (mA) 0.019 25 3.97 50 7.95 75 11.92 100 15.89 150 23.83
Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block).
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DS554 (v1.1) May 5, 2007 Product Specification
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XA2C128 CoolRunner-II Automotive CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VJTAG(2) VCCAUX VIN(1) VTS(1) TSTG(3) TJ Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground Voltage applied to 3-state output Storage Temperature (ambient) Junction Temperature Value -0.5 to 2.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -65 to +150 + 125 Units V V V V V V C C
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427.
Recommended Operating Conditions
Symbol VCC Parameter Supply voltage for internal logic and input buffers Industrial TA = -40C to +85C Q-Grade TA = -40 C to +105 C TJ Maximum = +125 C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V
VCCIO
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VCCAUX
Supply voltage for JTAG programming
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB ICC (1) CJTAG CCLK CIO IIL
(2) (2)
Parameter Standby current Industrial Standby current Q-grade Dynamic current JTAG input capacitance Global clock input capacitance I/O capacitance Input leakage current I/O High-Z leakage
Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V
Typical 60 60 -
Max. 200 1.5 2.0 12 10 12 10 +/-10 +/-10
Units A mA mA mA pF pF pF A A
IIH
Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block).
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LVCMOS and LVTTL 3.3V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage, Industrial grade High level output voltage, Q-grade VOL Low level output voltage, Industrial grade Low level output voltage, Q-grade IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V IOH = -4 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V IOL = 4 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Test Conditions Min. 3.0 2.0 -0.3 VCCIO - 0.4V VCCIO - 0.2V VCCIO - 0.4V VCCIO - 0.2V Max. 3.6 3.9 0.8 0.4 0.2 0.4 0.2 Units V V V V V V V V V V V
LVCMOS 2.5V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage, Industrial grade High level output voltage, Q-grade VOL Low level output voltage, Industrial grade Low level output voltage, Q-grade IOH = -8 mA, VCCIO = 2.3V IOH = -0.1 mA, VCCIO = 2.3V IOH = -4 mA, VCCIO = 2.3V IOH = -0.1 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V IOL = 0.1 mA, VCCIO = 2.3V IOL = 4 mA, VCCIO = 2.3V IOL = 0.1 mA, VCCIO = 2.3V Test Conditions Min. 2.3 1.7 -0.3 VCCIO -0.4V VCCIO - 0.2V VCCIO -0.4V VCCIO - 0.2V Max. 2.7
VCCIO +
Units V V V V V V V V V V V
0.3(1)
0.7 0.4 0.2 0.4 0.2
1. The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.
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DS554 (v1.1) May 5, 2007 Product Specification
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XA2C128 CoolRunner-II Automotive CPLD
LVCMOS 1.8V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH Parameter Input source voltage High level input voltage Low level input voltage High level output voltage, Industrial grade High level output voltage, Q-grade VOL Low level output voltage, Industrial grade Low level output voltage, Q-grade IOH = -8 mA, VCCIO = 1.7V IOH = -0.1 mA, VCCIO = 1.7V IOH = -4 mA, VCCIO = 1.7V IOH = -0.1 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V IOL = 4 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V Test Conditions Min. 1.7 0.65 x VCCIO -0.3 VCCIO - 0.45 VCCIO - 0.2 VCCIO - 0.45 VCCIO - 0.2 Max. 1.9
VCCIO
Units V V V V V V V V V V V
+ 0.3(1) -
0.35 x VCCIO
0.45 0.2 0.45 0.2
1. The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage.
LVCMOS 1.5V DC Voltage Specifications(1)
Symbol VCCIO VT+ VTVOH High level output voltage, Industrial grade High level output voltage, Q-grade VOL High level output voltage, Industrial grade High level output voltage, Q-grade
Notes: 1. Hysteresis used on 1.5V inputs.
Parameter Input source voltage Input hysteresis threshold voltage
Test Conditions IOH = -8 mA, VCCIO = 1.4V IOH = -0.1 mA, VCCIO = 1.4V IOH = -4 mA, VCCIO = 1.4V IOH = -0.1 mA, VCCIO = 1.4V IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V IOL = 4 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V
Min. 1.4 0.5 x VCCIO 0.2 x VCCIO VCCIO - 0.45 VCCIO - 0.2 VCCIO - 0.45 VCCIO - 0.2 -
Max. 1.6 0.8 x VCCIO 0.5 x VCCIO 0.4 0.2 0.4 0.2
Units V V V V V V V V V V V
Schmitt Trigger Input DC Voltage Specifications
Symbol VCCIO VT+ VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 3.9 0.8 x VCCIO 0.5 x VCCIO Units V V V
AC Electrical Characteristics Over Recommended Operating Conditions
-7 Symbol TPD1 TPD2 TSUD Parameter Propagation delay single p-term Propagation delay OR array Direct input register set-up time Min. 4.6 Max. 7.0 7.5 Min. 4.6 -8 Max. 7.0 7.5 Units ns ns ns
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XA2C128 CoolRunner-II Automotive CPLD -7 Symbol TSU1 TSU2 THD TH TCO FTOGGLE
(1) (2) (2)
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-8 Max. 5.4 300 152 141 119 112 7.3 7.5 8.5 9.9 8.1 7.6 9.0 350 4.0 2.0 0.0 Min. 3.0 3.5 0.0 0.0 3.1 1.5 2.0 0.2 1.0 3.5 0.0 1.6 7.5 7.5 0.0 6.0 Max. 5.4 300 152 141 119 112 7.3 7.5 8.5 9.9 8.1 7.6 9.0 350 Units ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us
Parameter Setup time fast (single p-term) Setup time (OR array) Direct input register hold time Hold time (Or array or p-term) Clock to output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Direct input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low Asynchronous preset/reset pulse width (High or Low) P-term pulse width High or Low Set-up before DataGATE latch assertion Hold to DataGATE latch assertion DataGATE recovery to new data DataGATE low pulse width CDRST setup time before falling edge GCLK2 Hold time CDRST after falling edge GCLK2 Configuration time
Min. 3.0 3.5 0.0 0.0 3.1 1.5 2.0 0.2 1.0 3.5 0.0 1.6 7.5 7.5 0.0 6.0 4.0 2.0 0.0 -
FSYSTEM1 FSYSTEM2 FEXT1(3) FEXT2
(3)
TPSUD TPSU1 TPSU2 TPHD TPH TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TAPRPW TPCW TDGSU TDGH TDGR TDGW TCDRSU TCDRH TCONFIG(4)
Notes: 1. FTOGGLE is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II Automotive CPLD family data sheet). 2. FSYSTEM1 is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while FSYSTEM2 is through the OR array (one counter per function block). 3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array. 4. Typical configuration current during TCONFIG is 10 mA.
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XA2C128 CoolRunner-II Automotive CPLD
Internal Timing Parameters
-7 Symbol Buffer Delays TIN TDIN TGCK TGSR TGTS TOUT TEN P-term Delays TCT TLOGI1 Parameter(1) Input buffer delay Direct data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single P-term delay adder Min. 1.4 0.0 1.6 0.0 Max. 2.6 5.3 2.1 3.5 3.0 2.6 4.5 1.4 1.1 0.5 0.7 2.5 0.7 1.5 3.4 2.6 4.0 1.0 4.0 4.0 0.0 4.0 Min. 1.4 0.0 1.6 0.0 -8 Max. 2.6 5.3 2.1 3.5 3.0 2.6 4.5 1.4 1.1 0.5 0.7 2.5 0.7 1.5 3.4 2.6 4.0 1.0 4.0 4.0 0.0 4.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TLOGI2 Multiple P-term delay adder Macrocell Delay TPDI Input to output valid TLDI TSUI THI TECSU TECHO TCOI TAOI
Feedback Delays
Setup before clock (transparent latch) Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Feedback delay Macrocell to global OE delay Hysteresis input adder Output adder Output slew rate adder Hysteresis input adder Output adder Output slew rate adder
TF TOEM THYS15 TOUT15 TSLEW15 THYS18 TOUT18 TSLEW18
I/O Standard Time Adder Delays 1.5V CMOS
I/O Standard Time Adder Delays 1.8V CMOS
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Internal Timing Parameters (Continued)
-7 Symbol TIN25 THYS25 TOUT25 Parameter(1) Standard input adder Hysteresis input adder Output adder Min. Max. 0.7 3.0 0.9 4.0 0.6 3.0 1.4 4.0 Min. I/O Standard Time Adder Delays 2.5V CMOS
-8 Max. 0.7 3.0 0.9 4.0 0.6 3.0 1.4 4.0 Units ns ns ns ns ns ns ns ns
TSLEW25 Output slew rate adder I/O Standard Time Adder Delays 3.3V CMOS/TTL TIN33 Standard input adder THYS33 TOUT33 TSLEW33 Hysteresis input adder Output adder Output slew rate adder
Notes: 1. 1.5 ns input pin signal rise/fall.
Switching Characteristics
VCC = VCCIO = 1.8V, 25oC
5.0
Switching Test Conditions
VCC R1
4.8
Device Under Test R2 CL
Test Point
4.6
TPD2 (ns)
4.4
4.2
Output Type LVTTL33 LVCMOS33
1 2 4 8 16
R1 268 275 188 112.5 150
R2 235 275 188 112.5 150
CL 35 pF 35 pF 35 pF 35 pF 35 pF
4.0
LVCMOS25 LVCMOS18 LVCMOS15
Number of Outputs Switching
DS093_02_050103
Figure 2: Derating Curve for TPD
Notes: 1. CL includes test fixtures and probe capacitance. 2. 1.5 nsec maximum rise/fall times on inputs.
Figure 3: AC Load Circuits
DS092_03_092302
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XA2C128 CoolRunner-II Automotive CPLD
Typical I/V Output Curves
3.3V
60
50
IO (Output Current mA)
40 1.8V 30
2.5V
Iol
20 1.5V 10
0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5
VO (Output Volts)
XC128_IV_all_050703
Figure 4: Typical I/V Curves for XA2C128
Pin Descriptions
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Pin Descriptions (Continued)
VQG100 CPG132 I/O Bank 13 12 11 10 9 8 7 6 4 3 G1 F1 F2 F3 E1 E2 E3 D1 D2 C1 C2 C3 2 2 2 2 2 2 2 2 2 2 2 2 Function Block 2 2 2 2 2 2 2 2 2 2 2 2 2(GCK0) 2(GCK1) 2(CDRST) 2(GCK2) Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQG100 CPG132 I/O Bank 14 15 16 17 18 19 22 23 24 27 G2 G3 H1 H2 H3 J1 J2 K1 K3 L2 M2 N2 1 1 1 1 1 1 1 1 1 1 1 1
Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1(GTS1) 1(GTS0)
Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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Pin Descriptions (Continued)
Function Block 3 3(GTS3) 3(GTS2) 3(GSR) 3 3 3 3 3 3 3 3 3 3 3 3 4(DGE) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 93 92 91 90 28 29 30 32 33 34 35 36 37 39 40 VQG100 CPG132 I/O Bank 2 1 99 97 96 95 94 B1 B2 A1 A3 B4 A4 C5 B5 A5 C6 B6 A6 C7 P2 M3 N3 P3 M4 M5 N5 P5 M6 N6 P6 N7 M7 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1
Pin Descriptions (Continued)
Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQG100 CPG132 I/O Bank 65 66 67 68 70 71 72 73 74 76 64 63 61 60 59 58 56 55 54 G13 G12 F14 F13 F12 E13 E12 D14 D13 D12 C14 B13 A13 H12 H13 J13 J12 K14 K13 L14 L13 L12 M14 M13 M12 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
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XA2C128 CoolRunner-II Automotive CPLD
Pin Descriptions (Continued)
Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQG100 CPG132 I/O Bank 77 78 79 80 81 82 85 86 87 89 C12 B12 A12 C11 B11 A11 C10 A10 C9 A8 B8 C8 B7 2 2 2 2 2 2 2 2 2 2 2 2 2
Pin Descriptions (Continued)
Function Block 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQG100 CPG132 I/O Bank 53 52 50 49 46 44 43 42 41 N14 N13 P14 P12 M11 N11 P11 P10 P9 M8 N8 P8 1 1 1 1 1 1 1 1 1 1 1 1
Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable. 2. GCK, GSR, and GTS pins can also be used for general purpose I/O.
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XA2C128 CoolRunner-II Automotive CPLD
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XA2C128 JTAG, Power/Ground, No Connect Pins and Total User I/O
Pin Type TCK TDI TDO TMS VCCAUX (JTAG supply voltage) Power internal (VCC) Power Bank 1 I/O (VCCIO1) Power Bank 2 I/O (VCCIO2) Ground No connects Total user I/O (including dual function pins) VQG100(1) 48 45 83 47 5 26, 57 20, 38, 51 88, 98 21, 25, 31, 62, 69, 75, 84, 100 80 CPG132(1) M10 M9 B9 N10 D3 P1, K12, A2 J3, P7, G14, P13 A14, C4, A7 K2, N1, P4, N9, N12, J14, H14, E14, B14, A9, B3 L1, L3, M1, N4, C13, B10 100
Notes: 1. Pin compatible with all larger and smaller densities except where I/O banking is used.
Ordering Information
Part Number XA2C128-7VQG100I XAC2C128-8VQG100Q XA2C128-7CPG132I XA2C128-8CPG132Q Pin/Ball Spacing 0.5mm 0.5mm 0.5mm 0.5mm JA (C/Watt) 47.5 47.5 72.4 72.4 JC (C/Watt) 12.5 12.5 15.7 15.7 Package Type Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Package Body Dimensions 14mm x 14mm 14mm x 14mm 8mm x 8mm Ind. (I)(1) I/O 80 80 100 Hi-T (Q) I Q I Q
Chip Scale 8mm x 8mm 100 Package; Pb-free Notes: I = Industrial (TA = -40 C to +85 C); Q = Automotive (TA = -40 C to +105 C with TJ Maximum = +125 C). Pb-Free Example: XA2C128 -7 VQ G 100 I
Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range
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XA2C128 CoolRunner-II Automotive CPLD
Device Part Marking
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Device Type Package Speed Operating Range
XA2Cxxx VQG144 7I
This line not related to device part number
Part Marking for all non chip scale packages
Figure 5: Sample Package with Part Marking Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale packages by line are: * * * Line 1 = X (Xilinx logo) then truncated part number Line 2 = Not related to device part number Line 3 = Not related to device part number * Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C6 = CPG132.
Figure 6: VQG100 Very Thin Quad Flat Pack
DS554 (v1.1) May 5, 2007 Product Specification
VCC I/O(2) I/O(5) I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O TDI I/O TMS TCK I/O I/O
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O(1) I/O(1) I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 GND I/O(2) I/O(2) I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O
GND I/O(3)
VCCIO2
VQG100 Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O VCCIO1
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - Data Gate
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XA2C128 CoolRunner-II Automotive CPLD
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VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O
P N M L K J H G F E D C B A
VCC GND
I/O(5) I/O(2)
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CPG132 Bottom View
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GND VCCIO2
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
Figure 7: CP132 Chip Scale Package
CoolRunner-II Automotive Requirements and Recommendations
Requirements
The following requirements are for all automotive applications: 1. Use a monotonic, fast ramp power supply to power up CoolRunner-II . A VCC ramp time of less than 1 ms is required. 2. Do not float I/O pins during device operation. Floating I/O pins can increase ICC as input buffers will draw 1-2 mA per floating input. In addition, when I/O pins are floated, noise can propagate to the center of the CPLD. I/O pins should be appropriately terminated with bus-hold or pull-up. Unused I/Os can also be configured as CGND (programmable GND).
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3. Do not drive I/O pins without VCC/VCCIO powered. 4. Sink current when driving LEDs. Because all Xilinx CPLDs have N-channel pull-down transistors on outputs, it is required that an LED anode is sourced through a resistor externally to VCC. Consequently, this will give the brightest solution. 5. Avoid pull-down resistors. Always use external pull-up resistors if external termination is required. This is because the CoolRunner-II Automotive CPLD, which includes some I/O driving circuits beyond the input and output buffers, may have contention with external pull-down resistors, and, consequently, the I/O will not switch as expected.
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DS554 (v1.1) May 5, 2007 Product Specification
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XA2C128 CoolRunner-II Automotive CPLD 2. Include JTAG stakes on the PCB. JTAG stakes can be used to test the part on the PCB. They add benefit in reprogramming part on the PCB, inspecting chip internals with INTEST, identifying stuck pins, and inspecting programming patterns (if not secured). 3. CoolRunner-II Automotive CPLDs work with any power sequence, but it is preferable to power the VCCI (internal VCC) before the VCCIO for the applications in which any glitches from device I/Os are unwanted. 4. Do not disregard report file warnings. Software identifies potential problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. Understand the Timing Report. This report file provides a speed summary along with warnings. Read the timing file (*.tim) carefully. Analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. Review Fitter Report equations. Equations can be shown in ABEL-like format, or can also be displayed in Verilog or VHDL formats. The Fitter Report also includes switch settings that are very informative of other device behaviors. 7. Let design software define pinouts if possible. Xilinx CPLD software works best when it selects the I/O pins and manages resources for users. It can spread signals around and improve pin-locking. If users must define pins, plan resources in advance. 8. Perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. Distribute SSOs (Simultaneously Switching Outputs) evenly around the CPLD to reduce switching noise. 10. Terminate high speed outputs to eliminate noise caused by very fast rising/falling edges.
6. Do not drive I/Os pins above the VCCIO assigned to its I/O bank. a. The current flow can go into VCCIO and affect a user voltage regulator. b. It can also increase undesired leakage current associated with the device. c. If done for too long, it can reduce the life of the device.
7. Do not rely on the I/O states before the CPLD configures. During power up, the CPLD I/Os may be affected by internal or external signals. 8. Use a voltage regulator which can provide sufficient current during device power up. As a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a CPLD in order to guarantee the CPLD can configure successfully. 9. Ensure external JTAG terminations for TMS, TCK, TDI, TDO should comply with the IEEE 1149.1. All Xilinx CPLDs have internal weak pull-ups on TDI, TMS, and TCK. 10. Attach all CPLD VCC and GND pins in order to have necessary power and ground supplies around the CPLD. 11. Decouple all VCC and VCCIO pins with capacitors of 0.01 F and 0.1 F closest to the pins for each VCC/VCCIO-GND pair. 12. Configure I/Os properly. CoolRunner-II Automotive CPLDs have I/O banks; therefore, signals must be assigned to appropriate banks (LVCMOS33, LVCMOS18 ...)
Recommendations
The following recommendations are for all automotive applications. 1. Use strict synchronous design (only one clocking event) if possible. A synchronous system is more robust than an asynchronous one.
Automotive Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
DS554 (v1.1) May 5, 2007 Product Specification
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XA2C128 CoolRunner-II Automotive CPLD
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Additional Information
Additional information is available for the following CoolRunner-II topics: * * * * * * * XAPP784: Bulletproof CPLD Design Practices XAPP375: Timing Model XAPP376: Logic Engine XAPP378: Advanced Features XAPP382: I/O Characteristics XAPP389: Powering CoolRunner-II XAPP399: Assigning VREF Pins To access these and all application notes with their associated reference designs, click the following link and scroll down the page until you find the document you want: CoolRunner-II Data Sheets and Application Notes Device Packages
Revision History
The following table shows the revision history for this document. Date 10/31/06 05/05/07 Version 1.0 1.1 Initial Xilinx release. Change to VIH specification for 3.3V, 2.5V and 1.8V LVCMOS. Corrections to tSUI, tECSU, tF, and tOEM for the -7 speed grade. Values now match the software. There were no changes to silicon or characterization. Revision
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DS554 (v1.1) May 5, 2007 Product Specification

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